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Symbiflow renames some primitives during symbiflow_synth. For example, an FDRE is renamed to be FDRE_ZINI. This causes spydrnet's function to find voter insertion points to come up empty.
For now I…
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HRef objects are meant to reference netlist objects (such as instances, ports, wires) by giving the hierarchical sequence to the object. This enables one to ensure they are accessing the correct objec…
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I am using sdn.parse() for parsing yosys edf outputs. Lots of circuits might have case sensitive wire names like 'n4139' and 'N4139'. In these cases, sdn.parse() merges these wires together which is w…
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Represent Xilinx built in primitives and provide functions for more easily dealing with Xilinx-specific primitives.
- Give the library ahead of time to the parser so that the parser checks against…
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A netlist output by the lattice tools (Synplify Pro specifically. It's actually a third party synthesis tool that can be used in lattice) lists the top module last in the netlist. SpyDrNet assumes the…
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Hi,
I'm using Atmel's fitter for the ATF150x parts, which can be made to generate an EDIF file, which I was hoping to parse with this project.
The first error I received was in regard to the tim…
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Here is the hierarchy structure of instances, and in the parentheses is the corresponding definition.
top
|- inst0 (Foo)
`- inst1 (Foo)
Foo
`- inv (INV)
The flatten function cannot hand…
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Yosys can produce EDIF but not read EDIF. It would be nice if EDIF reading support was added to Yosys.
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Thanks to JensRestemeier and Jordi1215 we have some example scripts that show how to create a netlist from the ground up in SpyDrNet. Now that we can create it would be nice to have some code to visu…
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Unsure if this actually applies to the project, as it probably doesn't come up in most (any?) netlists, but Verilog has the concept of primitives, both builtin (`XOR`, `AND`, etc), and [user generated…
agg23 updated
10 months ago