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Hello,
I want to use HDL AST to generate **Verilog (not System Verilog)**, but I am **worried that whether the converted file will have System Verilog specific syntax**. I see the class name in the …
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Currently in `clash-testsuite` we allow testing against `modelsim` for SystemVerilog only. However, we could allow testing against _all_ HDL supported by Clash in `modelsim`, which would help identify…
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### Description
Hello! While writing a custom step I'm facing the challenge to inject custom Verilog into the flow.
By this I mean the ability to add new files to the `VERILOG_FILES` variable. Unf…
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It would be great to support the open source FPGA tooling from https://f4pga.org/ project. Examples on how to use the tooling for Xilinx 7 series parts can be found here -> https://f4pga-examples.read…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
2 months ago
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> ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/functions.vh:44]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in ver…
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how to configure Verilog/System Verilog to support in Emacs lsp-mode?
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First links to documentation pages:
https://www.intel.com/content/www/us/en/programmable/quartushelp/22.1/index.htm#hdl/vlog/vlog_list_sys_vlog.htm
https://www.intel.com/content/www/us/en/programmab…
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It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
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