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Hi everyone,
I am trying to simulate a design containing some Altera IPs but for all of the IPs GHDL give me a warning `"instance "IP" of component "IP" is not bound"`. So, I just created a PLL and…
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* [x] Prepare release branch
* [x] Check clean Git History
* If not, clean-up history by rebasing
* [x] Run coverage simulations locally -> Check 100% coverage
* [x] Test tutorial builds
* [x…
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I needed to simulate the gate level netlist for DFFRAM, but I found that no combination of defines results in functional results with icarus verilog and sky130_fd_sc_hd.v as installed by Open_PDK. De…
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Hi All,
We were wondering if it would be possible to support a flag in `firtool` that uniquifies the modules under the `Dut` and `Harness`. When running timing annotated simulations, after the `Dut…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
1. clone chisel template
2. run `sbt test`
3. it fails
**What is the current behavior?**
I traced…
zhc7 updated
5 months ago
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Hi,
I am trying to verify the ramulator memory controller and DRAM model as explained in the README.
I am using ncsim (ncverilog) as a simulator - ddr4_verilog_models/protected_ncverilog-
I mo…
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**Hosting details :**
- **Hosting Unit(Lab) Name** : Very Large Scale Integration Lab (VLSI)
- **Repository URL** : https://github.com/virtual-labs/vlsi-iiith
- **Branch/Tag** : master/[v1.1.3](h…
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Would you be able to add a LICENSE / COPYING file to this repo? I'm interested to know what license you are releasing these under.
It would also be good to know how you created these simulations of…
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I'm getting the following message:
//////////////////////////////////////////////////
Compiling /home/xxxx/Downloads/Opencore/orpsoc-build/build/atlys/src/elf-loader/elf-loader.c...
Compiling /home/x…
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Thanks for taking the time to report this.
What would you like added/supported?
Improve FST tracing performance
What 'verilator --version' are you using? Did you try it with the git master ver…