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BSC can automate the linking of a Verilog simulation for a number of simulators. We should add Verilator to that list:
```
bsc -e topMod -verilog -vsim verilator
```
Basic support will require …
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**Impact**: simulator
**Tell us about your environment:**
*Chipyard Version:* 1.4.0, Hash 58076c
*OS:* Linux ubuntu 5.8.0-40-generic #45~20.04.1-Ubuntu SMP Fri Jan 15 11:35:04 UTC 2021 x86_64 x…
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To make sure to not accidentally introduce memory leaks or invalid memory access issues, we should run the tests with AddressSanitizer in the CI (maybe as separate after successful 'regular' testing, …
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Our simulator makefiles get the list of Verilog and VHDL sources in separate variables, and in ``Makefile.questa``, ``Makefile.aldec``, ``Makefile.activehdl``, there are separate compiler calls to com…
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Support for setting module parameters should be added. Different simulators need module parameters passed through in different ways - different command line switches are used, and some require them i…
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I wanted to make verilator the default verilog simulator for fud, so I set the `stages.verilog.priority` key to 1. This works, but causes a warning saying that the key is unknown. I don't think that t…
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paramsets were added to Verilog-A in version 2.4 for two reasons:
1. to provide a Verilog-A/MS native way to specify the information normally provided by the SPICE .model cards (this was considered…
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Hi. It is my first time using cocotb with Xcelium (always GHDL or iverilog). Has far I understand it must work, but fail.
* the cocotb version used: 1.5.2
* the operating system and version: Cento…
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### Is there an existing issue for this?
- [X] I have searched the existing issues
### Describe the bug
Input `pre` is not used in the Verilog code for `DflipFlop`.
```verilog
module Dfli…
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This will allow us to portably build the tests for different verilog simulators so that people can more easily use the tests.