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RISC-V ISAs provide a set of up to 32×64-bit performance counters and timers.
RV32I provides a number of 64-bit read-only user-level counters, which are mapped into the 12-bit CSR address space and…
jserv updated
2 years ago
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### Description
When I passed the parameters about verilog_files in config.tcl, I found that the absolute path, or the same way of passing parameters as in json caused the file to not be found, I w…
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starting from picorv32, we want to use asynch reset and maybe convert it to systemverilog
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To generate the RISCV firmwares for BARVINN simulation, I am trying to compile the convolution C code in `csrc/conv/` . So I installed the rv32 RISCV compilation toolchain as per the Picorv32 [instruc…
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We currently don't support LiteX master (as of 2022-08-24), with `dma_test` resulting in an instantaneous reboot, even without a kernel panic (i.e. no crashdump). The 2022-04 tag works, as does the fo…
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To reproduce:
```
cd examples/picorv32_primes
mcy init
mcy run
```
1. sby is now requiring a `[tasks]` section with regex (https://github.com/YosysHQ/sby/issues/76), but this wasn't added to `…
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您好。我跑起来了。
就是串口通信 进了shell。。。
问题就是我不知道sdram模块是不是正常工作。。。rtthreader里面好像也没有检测sdram的函数
还有就是我的时钟是24m。我改了pll。运行在72m没有问题。
现在就是我想用里面的sdram模块。。。代码比较晦涩。。。所以我问一下
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Hello,
just for info, the initial Raptor build backend for LiteX is available at https://github.com/enjoy-digital/litex/tree/master/litex/build/osfpga.
Two designs have been created:
- `test_bl…
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I'm trying to add riscv-formal to my core and while running it, I'm getting:
```sh
❯ ./start_formal.sh
Reading checks.cfg.
Creating checks directory.
Generated 43 checks.
make: Entering direct…
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Question1：
Why is the state of FSM and Emun defined with define? This introduces hidden risks, for example:
There are 3 verilog files, a.v, b.v and c.v. The synthesizer reads the files in sequence, …