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The power pins 'VPWR', 'VGND', 'VPB' and 'VNB' are mainly used by physical design tools, which are not needed when doing functional verification.
When developing RTL for a chip, users are supposed no…
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### Description
The S-> X IOPATH of MUXes are duplicated in the SDF file and have different values:
SDF file snipset:
(CELL
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
(INSTANCE _344_)
(…
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```
(gdb) bt
#0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50
#1 0x00007f431811f537 in __GI_abort () at abort.c:79
#2 0x00007f4318178768 in __libc_message (action=action…
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I run a simple `openlane2` trial run. When the flow finished, I checked the final gds file using
```bash
openlane --last-run --flow openinmagic designs/dff/config.json
```
The flow instantiates …
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Version `8.3.392`
There are 7 m4-m5 mimcaps in the design 1 is 6.88x6.89, 3 are 2x2, and 3 are 1x1.
The 1x1 capacitors extract with a floating top net.
```
X11 c2_7893_4697# a_6172_2126# sky13…
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Hello！Magical is a good job ！ Now we want to use MAGICAL to realize the circuit designed by CSMS 250nm process, but when we change modify mock.techfile and techfile.simple in mockfile，it will report i…
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## Expected Behavior
No Via resistance in tech lef
## Actual Behavior
Via resistance in tech lef
## Steps to Reproduce the Problem
1.
1.
1.
## Specifications
- Version:
- Platform:
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I have an issue when try to simulate the Reram-tb utilizing xscehm and ngspice. I encounter the following errors when trying to simulate the reram and check the waveform uisng ngspice: % l_s_d(): Symb…
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First, thank you for your great work on qflow, Magic, ... !
I resurrected the SPICE model collection originated in ancient MOSIS MPW runs. Some of the models are related to qflow/OSU technology use…
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Is the final schematic included in the repo?
I'm working on trying to rerun your sims and couldn't find the schematic shown in your readme.
The schematics that start with "tsmc" in "/schematics"…