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As mentioned in its documentation, the synthesis attributes are an experimental feature, and I have found several cases where it does not work as I would expect with Clash from last week's git master …
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Hello!
How can I deal with the input and output if I want to use this in my FPGA?
I tried to plan the pin but the data line is always high, is there any input required?
Thanks a lot!
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When working in Atheos I see at regular intervalls that the screen is updating and textfiles with property vhdl or asciidoc are set back to text. Any context menu open at this time disappears and the …
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Hi Nic30:
Is it possible to instantiate a VHDL or Verilog IP as a black-box component like [Spinalhdl](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Structuring/blackbox.html)? Thanks.…
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when running emacs on windows without wsl, the formattter seems to do nothing.
Output in the VHDLbyHGB.emacs-vhdl-format:
> Debugger entered--Lisp error: (end-of-file)
> command-line-1(("--eva…
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Option `compile_builtins` of methods `from_args` and `from_argv` is to be removed in an upcoming release of VUnit. Until v4.7.0 (included), compile_builtins is enabled by default. Therefore, removing …
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I have a case where a VHDL entity (say vhdl_top) is instantiating a Verilog module with upper-case letters (say VERILOG_MODULE):
VERILOG:
```
module VERILOG_MODULE (
.....
endmodule
```
T…
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When will support for VHDL be added (`.vhd` and `.vhdl`)? I would guess this is similar to Ada, so probably not much work there. SystemVerilog (`.sv`)should be the same as verilog.
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Add support for bringing VHDL types into Python.
The obvious ones are enumeration and physical types.
**Enumeration type**
```vhdl
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGU…
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VHDL process details which were specified inside a process aren't in output.
Particularly global scope tags like \todo and self-written aliases get lost.
The attached example was generated with …