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Hi,
I am currently working on a custom RISC-V core and came across this project, and I was wondering if there exists/ are any plans for guidance on how to swap out the existing CPU with a different…
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I'm trying to connect iob_cache directly to a picorv32 core. But I noticed that, when reading from certain address, the `rdata` turns to be 'x'. It happens when the `addr[3:0] == 4'b0000`.
![image]…
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Hi Marcelo,
I have read these new codes which are commited recently.
I am confusing about NXPC2[2] thing, which index 0 and 1 represent different threads if I am right.
And in C codes, 'int tmp =…
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Hi,
I've looked at the project and seen it is based on the https://github.com/YosysHQ/picorv32 which can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contain a bui…
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is there any good documentation/papers that you can refer to? or is it best to just "read the code",
google gave me this: http://fpga-guru.com/files/supercn.pdf
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Hello, does anyone have problems compiling the firmware from the lab004?
I'm using KDE Neon based on Ubuntu 18 and the last Litex and RiscV toolchain version, my target is an arty_s7.
When I try t…
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**Is your feature request related to a problem? Please describe.**
[LiteX](https://github.com/enjoy-digital/litex) is an excellent System on Chip build environment [that supports many different sof…
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can picorv32 run on iCE40UP5k start basic firmware
https://github.com/cliffordwolf/picorv32/tree/master/scripts/icestorm
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## Problem
The current [PICORV32](https://github.com/IObundle/iob-picorv32) does not support missaligned accesses to memory.
## Example
Here is an example of a program that shows the issue:
```C…
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