-
Hello,
I am wondering how I can debug a C program using Verilator and riscv-gdb on Core SweRV EH1.
Do I need openOCD and JTAG to bridge Verilator and riscv-gdb? I saw people imitate a JTAG by wri…
-
HI !
Is there a problem with the linker when running a c code ?
My c code includes all the necessary librarys and compiles separatly without a problem but i try to run it using the core , I keep…
-
Hi,
I have managed to perform all of the steps of the read me document and test the hello World.
I was wondering on what is the correct way to run my own written c program on the SweRV core ?
…
-
Hi,
Thanks for the repository.
I got this error in Vivado 2020.1:
[HDL 9-849] Syntax error : file ended before end of clause. ["../Cores-SweRV-EL2/snapshots/default/el2_param.vh":156]
Seems like…
-
I ran this on a clean checkout:
make -f $RV_ROOT/tools/Makefile target=default_mt debug=1
I am getting the following error:
VerilatorTB: Start of sim
terminate called after throwing an instanc…
-
> So cmark scores are dependent on which version of the compiler you use and which flags.
>
> Give the command below a try. With gcc 9.3 this yielded CM 3.61.
>
> Thanks.
>
> run.int make -f…
-
I got error messages as below when running simulation with target=high_perf.
default target has no problem but high_perf target has the problem.
Please help me.
[config & simualtion]
configs/swe…
-
How can I know when the core is stalled when running? is there a way for me to display/know the cycle when the core is stalled?
Thanks in advance
-
Hi,
I try to simule a small file.c that it uses standard libraries (stdio).
For example to use printf from stdio:
```
#include
#include "defines.h"
#define ITERATIONS 1
extern int STACK;
…
-
hi,
l saw some infomation in README.md .:"If adding/removing instructions, espresso must be installed (used by tools/coredecode)".
Can this increase the custom instructions ，and how to use this sc…