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This looks like a very interesting project (I develop a VPNish routing software called cjdns which uses salsa20/poly1305) but I was wondering if you had carried out any benchmarks and whether you have…
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**Description**
After compiling ALL Xilinx libraries I discovered that a lot of in the XIlinx libraries available components are not compiled in the GHDL libraries.
Maybe I'm doing something wrong? …
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Hey,
Thanks for the amazing work.
I haven't found any other appropriate place to ask this and I have absolutely no idea how the fabrication works. How many transistors, approximately, does Hazard3 c…
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LiteX supports multiple CPU architectures, lets try and support all of them!
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Some hard CPU cores (Zynq-7000, EOS S3) do address translation on peripheral buses - say for the CPU addresses of a bus start at 0x40020000 and CSR_BASE C definition has to have that value, but the ad…
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- [ ] Blinky
- [ ] Counter
- [ ] Ibex
- [ ] LiteX?
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# Bug Report
## One-Line Summary
Unexpected behavior for clock configuration.
## Issue Details
### Steps to Reproduce
* First confirm that some clock options do work.
* ``` $ a…
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Hello,
I'm trying implement this on Zynq Ultrascale with directly connecting to AXI buses.
Do it need additional changes in design to accept such connection?
Did you tried such implementation ?
…
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Not certain how you want these, but I keep having this kernel error pop up on every boot. Using an Up2 board with NV4200. Primarily using default kernel options from meta-intel and meta-up-board, with…
dv01d updated
5 years ago
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# 总结
- https://github.com/cliffordwolf
- https://github.com/wuxx/icesugar
- https://github.com/icebreaker-fpga/icebreaker
- http://www.elecfans.com/pld/838620.html
cisen updated
3 years ago