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Is there any way to add clocks generated with ecppll to ghdl? Is there any other generator? Is there any examples somewhere?
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Hi. It seems that since https://github.com/ghdl/ghdl-yosys-plugin/issues/98, `ghdl/synth:beta` and `ghdl/synth:formal` has been not generated. Both of them are 14 days outdated (the change was 9 days …
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Here you have two examples from ISE, which are synthesized by `ghdl --synth` but fail with the plugin (same error, with a different `` value): [tdps.zip](https://github.com/ghdl/ghdl-yosys-plugin/file…
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Hi @tgingold, I know that you are still working with the inference of BRAMs. There are several examples from Xilinx, but only four of them fails with ```ghdl --synth``` (and probably also #1244 when s…
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The plan a couple of months ago was to do a major bump of GHDL to version 1.0, which would involve moving synthesis features out of beta. By the end of february we were not there yet, so Tristan decid…
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In synthesis assigning a record; with another record signal in the assignment; it seems like the record becomes bit-reversed.
Consider:
```vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use ie…
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I was [verifying GHDL `--synth` and the `ghdl-yosys-plugin` with examples from Xilinx](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers). I found a problem with a file for ISE, called *…
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I was [verifying GHDL `--synth` and the `ghdl-yosys-plugin` with examples from Xilinx](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers). I found a problem with a file for ISE, called *…
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When running `make` I'm getting the following error message:
```
src/ghdl.cc: In function ‘void import_module(Yosys::RTLIL::Design*, GhdlSynth::Module)’:
src/ghdl.cc:570:59: error: no match for c…
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## Steps to reproduce the issue
Standard build of SNES_MiSTer_ulx3s
```
git clone https://github.com/daveshah1/SNES_MiSTer_ulx3s
cd SNES_MiSTer_ulx3s
cd ulx3s/scripts
bash build.sh
```
out…