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`DEFINE PORT GROUP` and `IOBUF GROUP` can be used to specify default attributes to all ports in a group and the attributes can then be overridden as needed. Right now `DEFINE` statements are silently …
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Hi !
With the new xilinx changes (HEAD) using latest prjxray & prjxray-db leads to build error.
Seems that ```kintex7/timings/slicem.sdf``` was never present in the public [prjxray-db](https://g…
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It would be interesting for setup-msys2 to support a third source type. Apart from the built-in installation or a clean release, it would be convenient if users could provide their own tarball/artifac…
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I use ghdl plugin for parsing VHDL code to be synthesized with Yosys to iCE40.
GHDL 2.0.0-dev (1.0.0.r73.g691be6df)
Yosys 0.9+4008 (git sha1 396ad17e, gcc 10.2.0-13ubuntu1 -fPIC -Os)
My library…
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Hi @sylefeb!
Are you aware of the `mingw-w64-*-eda` tool groups in upstream MSYS2 repositories? That one is available for all environments (MINGW32, MINGW64, CLANG32, CLANG64 and UCRT64). See the l…
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When explicitly instantiating a cell, all the IOs need to be explicitly stated, or otherwise an invalid DCP is generated, where the cell results to be unplaced, despite being present in the physical n…
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I am trying to build a project for a CrossLink-NX device.
The following is being executed by the makefile:
```
pushd /home/noxet/dev/sdi-mipi-video-converter-fpga-design/build/1080p_3g-2lanes && …
Noxet updated
1 month ago
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[ERROR_Failed_to_route_arc_0_of_net_modules_2_mem_ext_Memory_0_8_genblk1_genblk1_CAS_B.zip](https://github.com/user-attachments/files/16709343/ERROR_Failed_to_route_arc_0_of_net_modules_2_mem_ext_Memo…
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I am implementing a large circuit on OpenFPGA and when in VPR step, it tooks a lot of time (particularly 222590 seconds) to run. In vtr documents, I see that there is a option to optimize my circuit b…