chipsalliance fpga-interchange-tests issues

chipsalliance / fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

https://chipsalliance.github.io/fpga-interchange-tests

ISC License

8 stars 9 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

ci: update custom runners labels

#134 kgugala closed 1 year ago
0
Add building data for NISP

#133 mkurc-ant closed 1 year ago
2
Bump the python-fpga-interchange submodule

#132 mkurc-ant closed 1 year ago
0
Upload interchange data to GCP with GitHub Actions

#131 rw1nkler closed 2 years ago
2
Add set -e to setup bash scripts

#130 tmichalak closed 2 years ago
0
Add UHDM/SystemVerilog support and test

#129 kboronski-ant opened 2 years ago
0
[nextpnr-fpga-interchange] Improve place and route runtime

#128 clavin-xlnx opened 2 years ago
0
Error trying to convert xcvu095-ffva2104-2-e.device to json

#127 zhilix opened 2 years ago
1
[nextpnr-fpga-interchange] Incorrect LUT INIT causing CRITICAL WARNINGS in Vivado

#126 clavin-xlnx opened 2 years ago
0
[nextpnr_fpga_interchange] Failure in placement

#125 clavin-xlnx closed 2 years ago
3
[nextpnr_fpga_interchange] Fails to properly place and route a design with hierarchy

#124 clavin-xlnx opened 2 years ago
0
[nextpnr_fpga_interchange] Fails when encountering unsupported XDC commands, provides warnings for others

#123 clavin-xlnx opened 2 years ago
0
[nextpnr_fpga_interchange] ERROR: Assert ctx->checkRoutedDesign() failed

#122 clavin-xlnx opened 2 years ago
0
A Tcl script that can take an arbitrary netlist and use Vivado to create pin placements

#121 clavin-xlnx opened 2 years ago
0
[nextpnr_fpga_interchange] Proceed with place and route despite missing pin placement constraints

#120 clavin-xlnx opened 2 years ago
0
cmake: add target to run all dcp generation for xilinx archs

#119 acomodi closed 2 years ago
0
Refactor CI to add centOS 7

#118 acomodi closed 2 years ago
0
WIP: test centos7

#117 acomodi closed 2 years ago
1
[BOT] Conda Lock Update

#116 github-actions[bot] opened 2 years ago
0
[BOT] Conda Lock Update

#115 github-actions[bot] closed 2 years ago
0
Run cron CI

#114 acomodi closed 2 years ago
0
Cannot run test suite in CentOS Linux 7.4

#113 clavin-xlnx closed 2 years ago
6
docs: theme s/SymbiFlow/F4PGA/

#112 umarcor closed 2 years ago
0
Bump python-fpga_interchange

#111 kboronski-ant closed 2 years ago
3
Bump python-fpga_interchange

#110 kboronski-ant closed 2 years ago
0
tests: zcu104: add murax test

#109 acomodi opened 2 years ago
1
Bump python-fpga_interchange version

#108 kboronski-ant closed 2 years ago
0
PLLE4 test for ZCU104

#107 kboronski-ant closed 2 years ago
1
DCP generation fails for some tests

#106 acomodi closed 2 years ago
4
Bump RapidWright

#105 acomodi closed 2 years ago
0
results: fix plot graph in web report

#104 acomodi closed 2 years ago
0
Add tests for Kintex-7

#103 robertszczepanski closed 2 years ago
0
enable a public GCP bucket to store the device data and chipdb

#102 acomodi opened 2 years ago
5
WIP: ci: gh: initial code to upload artifacts to GCP

#101 acomodi closed 2 years ago
1
Add tests for Spartan 7

#100 robertszczepanski closed 2 years ago
0
Add US+ BRAM test

#99 kboronski-ant closed 2 years ago
1
Feature tests for Ultrascale+ (failing on not placeable element)

#98 kboronski-ant closed 2 years ago
3
Feature tests for Ultrascale+ (hanging on analytical placer)

#97 kboronski-ant closed 2 years ago
1
Feature tests for Ultrascale+ (failing due to no route)

#96 kboronski-ant opened 2 years ago
0
BELs bound to multiple pads on Ultrascale+

#95 kboronski-ant closed 2 years ago
1
fasm2bels tests failure to read DCP in Vivado

#94 acomodi closed 2 years ago
4
Feature tests for Ultrascale+

#93 kboronski-ant closed 2 years ago
7
Bump RapidWright version

#92 kboronski-ant closed 2 years ago
0
Use Rapid YAML from PyPi

#91 tmichalak closed 2 years ago
0
Add VPR initial test

#90 acomodi closed 2 years ago
0
tests: remove retarget from LiteX tests

#89 acomodi opened 2 years ago
0
tests: add cell to bel mapping in test arch

#88 acomodi closed 2 years ago
0
LUT-thru tests

#87 mkurc-ant opened 2 years ago
0
GH action: add conda bot lock

#86 acomodi opened 3 years ago
0
testarch: remove LUT definitions patching step

#85 acomodi closed 3 years ago
0