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I'm using the cocotb Clock class to drive the clock in my design. Which I fork in this test:
```python
@cocotb.test()
async def test_alu(dut):
clock = Clock(dut.clk, 2, units="us")
coco…
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I haven't made as much progress on this as I'd like over the last couple weeks, so creating a feature request issue to keep it on my list and put down what I've thought about so far.
The feature re…
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In my examples of using moore to generate LLHD, I can't successfully generate the reg primitive. I expected a SystemVerilog reg to generate a LLHD reg, but that did not happen for me. Can someone prov…
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I am trying to use verilator on the .sv (or .v) output from Clash, the high level HDL. Clash has successfully generated netlists and .sv files in Test/TestBench/ but when I run verilator .. -ITest/Te…
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I’m getting a fatal error when running a basic testbench with VHDL under Cadence’s Xcelium simulator. Using this exact testbench with an equivalent Verilog or SystemVerilog design works perfectly …
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Hello,
I am using Icarus Verilog for simulations using cocotb testbench. The iverilog version is 11.0 stable. Running on Ubuntu 18.04LTS.
I get an error when I run the simulation on Icarus Veril…
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Hi,
I'm very interesting to use your language server with the brand new LSP of Neovim. I made a pull request here:
https://github.com/neovim/nvim-lspconfig/pull/477
However, even of the serve…
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Hello,
I generated a netlist using Design Compiler.
I have two issues:
1. In sp_ram_wrap.sv is a module called 'sp_ram_bank' but there is no file containing this module. Where can I find it?
2. I …
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Many of the basejump tests don't work correctly as standalone tests. They reference modules from other files that aren't included in the tests, for example. Most annoyingly, they default all module pa…
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```
./cyclone_ep4ce10.py --cpu-type=cv32e40p --cpu-variant=standard --integrated-rom-size=0x8000
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / …