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It needs no special components, just wires!
Code snippet
```
class _CRG_arty(Module…
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Hello,
I'm getting errors while generating Arty bitstream and I'm using docker image. can someone give me a hint?
> root@0daba79434b7:~/chipyard/fpga# make SUB_PROJECT=arty bitstream
Running…
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Hello @tcal-x
I am using the Digilent Arty board containing the 100T device with the CFU Playground on the default **proj_template** example.
With the following command line, I see the followin…
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I'm currently working on adding a custom instruction to acceleration AES in the SMP branch.
```
SoC configuration :
./make.py --board=arty_a7 --cpu-count=2 --dcache-width=64 --icache-width=64 --d…
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I'm using the command
`podman run --rm -it -v /$(pwd)://wrk --security-opt label=disable -w //wrk gcr.io/hdl-containers/conda/f4pga/xc7`
and was able to build without issues. However, flashing/d…
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I am trying to run the arty-100t-nic project.
_Run server-start.sh to start the wishbone bridge.
_Run dump.sh which waits til a network packet is completely received and then creates a *.vcd capt…
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Hi there,
Thanks a lot for your work!
I tried to use symbiflow toolchain and I couldn't make it work.
I am using current master branch revision for litex-boards and linux-on-litex-vexriscv.
…
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I wanna build an SoC with the digilent art a7-100 as the target. When I tried building the target file, I faced an error like this:
File "/home/pkanthamraju/litex/litex/litex/build/xilinx/vivado.py…
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Hi,
I read a comment in another thread that a more up-to-date CEP will be migrating to UCB'sChip Yard.
Is there a time frame when the migration could happen? I am interested in using the most-up-to-…