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I have issue with diode example (from tutorial):
var netlist = string.Join(Environment.NewLine,
"Diode circuit",
"D1 OUT 0 1N914",
"V1 OUT 0 0",
…
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I am trying to model following test circuit and I am confused what would be the way of programming it in SpiceSharp specially values and function that are used here: Exm , Guv.
Please advice
I_M …
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FDRE_0 : FDRE
generic map(
INIT => X"0"
)
port map (
C => signal_0,
CE => signal_104,
D => signal_12,
R => signal_103,
Q => signal_99
);
has to be... INIT => …
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Hello guys,
I’ve compiled and ran this whole project under x86_64 before, it was successful, it’s a very nice project for IC designers like me, thank you very much!
Now I’m trying to compile the…
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## Current Behaviour
segfault when accessing 2d arrays in local param table
## Possible Solution
check sc_spot is not negative
## Steps to Reproduce
see bellow
## Context
tried to compile…
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Author Name: **Udi Finkelstein**
Original Redmine Issue: 1429 from https://www.veripool.org
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While looking for a way to trigger an error on invalid parameter combinations of a parammetriz…
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Author Name: **Jack Langsdorf**
Original Redmine Issue: 1428 from https://www.veripool.org
Original Assignee: Jack Langsdorf
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Installing Verilog::Netlist or Verilog::Parser (etc) from C…
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if we keep pugixml in compact mode using the define
https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/b2807fadc3495fcfe82e4e8d5bfcc9662ada6493/libs/EXTERNAL/libpugixml/CMakeLists.tx…
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### Environment (OS, Python version, PySpice version, simulator)
Ubuntu 16.04, Python 3.6.5, PySpice 1.2.0, ngspice 26 as subprocess
### Expected Behaviour
This is a SPICE netlist file for a …
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To use the framework you have to have a DEF file so that the physical design information be filled in the rsyn framework. Using tools like qflow to input a verilog file and synthesize it to a netlist …