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Hart.cpp is missing an
#include \
FpRegs.hpp is missing
#include \
which makes it fail to compile on my system
CentOS 7
gcc 10.2.0
boost 1.74.0 c++17
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Setting a store address & value breakpoint using chained triggers succeeds in setting and reading back the mcontrol registers if triggers 1 & 2 are used, but the breakpoint is hit on instructions whic…
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**Describe the bug**
After activating `LOG_BACKEND_FS`, `CONFIG_FILE_SYSTEM_LITTLEFS` and their dependencies, it worked as expected on the very first time boot (clean storage partition).
The probl…
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Hi, all,
It seems standard OpenOCD can not access ICCM/DCCM, how to enable it?
There some information mentioned here, Anyone has the detail information?
Thanks.
SweRV_CoreMark_Benchmarking…
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I have generated interrupts tests using "riscv_full_interrupt_test" test from base_testlist.yaml. I am using rv32imc as target. However, I am unable to run them successfully on SweRV core. On simulati…
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Hi, after some changes my code is working on SwerVolf 0.7 and external interrupts are configured, the handler is correctly identified. However, I am unable to clear the pending bits of the external in…
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Hello, can you point which JTAG you using for this project? There are many old JTAG ports on that site.
Thank you,
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Hi !
I have been trying to the make -f $RV_ROOT/tools/Makefile
and the verilator build is failing .
but when i run the verilator is installed in my ubuntu system and the commands works se…
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I tried to run the swerv core with Configure in "SweRV_CoreMark_Benchmarking.pdf" on genesys2 fpga board, and it could successfully run the hello example through openocd;
But when I tried to run the …
wehob updated
4 years ago
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I am not completely sure that I have it right, but wanted to report it to see if there's a usage issue or an sv2v issue. The attached package file is not converting - sv2v produces an empty output. Ve…