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Hello @mithro and @eine.
I think that you both know very well the FOSS ecosystem, but I know that you have predilections :P (Verilog and VHDL, of course). Would you check the following categorized …
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So we do need permissive and its even slightly different for verilator so its good that its overrideable:
```
simulator-example-RocketConfig +max-cycles=5000 +verbose -- +permissive +verilator+V +pe…
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Hi @rodrigomelo9,
This type of project seems like it would be an excellent addition to the SymbiFlow project. Did you want to join forces here?
The rest of the SymbiFlow project is using the fol…
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Hi,
I'm currently working on a project with the rocket core. We're trying to run some come code bare-metal and doing simulations using the VLSI flow. My question is, how are the programs loaded into…
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In many of my state machines, I have asserts inside the `bla = new State { whenIsActive {` block to check for conditions that should hold in this specific state.
Sometimes in simulations, these ass…
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hello
i have used the chisel generator to create a rocket chip, but the top modules is called "TestHarness". additionally i found "DPI-C" stuff in the generated verilog code. this makes it look lik…
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**NOTE** this task will not be started until issue [#52](https://github.com/openhwgroup/core-v-verif/issues/52) is complete.
### Task Outcome
Update our simulation Makefile (and perhaps some support…
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Below is what I brought up on Gitter :) The questions asked point to places, where new diagnostics could be printed.
I have set up a number of simulations for a component of mine and I have trouble…
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I am trying to use your rtl at the integration exercise in order to feed it to our project OpenFPGA.
Even with the help of one of your students I am having issues getting the Verilog needed for our…
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Hello everybody,
I'm rather new to the NetFPGA system, so bare with me if I made some mistakes. Currently I'm stuck at getting reference projects running on the NetFPGA 1G CML board. I can program …