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This is almost certainly an issue with XIlinx, but I wanted to point out that I am seeing a Vivado Simulator Failure when running a simulation with a generated register block:
FATAL_ERROR: Vivado S…
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Thanks for help.
I am just setup my new study environment.
After I use command `make TEST=riscv_machine_mode_rand_test ITERATIONS=1 SIMULATOR=vcs`, terminal just report this:
```
Build metad…
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Hi @michael-platzer , @stevobailey , @kuoyaoming93 , @moimfeld
I tried to add a config to `config.mk` file but in spite of the @michael-platzer help, I couldn't get the result when implementing on F…
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Hi Skatanik,
At first, thanks for you code. it seems very helpful.
Sorry for my trivial question, I am interested to run the code on digital simulator to understand the DSI controller part (the Prot…
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Following the guide in readme.md to generate bitstream for zc702_fmcs2 board with code version 8cdaf54. No any code change. It fails.
Host OS: Ubuntu LTS 22.04 with Vivado Simulator 2018.3
Below i…
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Hello Community
Is there any user documentation which explains basic flow of the "iob-cache" and how can we understand it.? I am getting perplexed with files getting generated after verilation in ob…
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Currently, if `VUNIT_SIMULATOR` is set to 'questa' the following error occurs:
> RuntimeError: Simulator from VUNIT_SIMULATOR environment variable 'questa' is not supported. Supported simulators ar…
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## Observed Behavior
I run `make TEST=riscv_machine_mode_rand_test ITERATIONS=1 SEED=1 COV=0 SIMULATOR=xlm` in `dv/uvm/core_ibex`. The terminal outputs:
`mkdir -p out/build
make: *** [Makefi…
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I want to know the wave in hardware simulation in shared-vadd.
So I use the code in https://tapa.readthedocs.io/en/release/tutorial/fast_cosim.html?highlight=vivado#view-waveform
`./vadd -xosim_sa…
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I want to simulate the simple system example using VCS, the build passes without any issue, but when I run the simulation, I get multiple errors caused by failed assertion
## My Environment
…