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Hi,
Since v10.2 one further simulation step seems to be required for continuous assingments inside *always* procedure, and not for the same logic described with *assign*.
Link to testcase: https://g…
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(Original issue 1201 created by kraigher on 2016-01-26T19:25:49.954371+00:00)
The lexer fails on a SystemVerilog code snippet that contains calls to the `$info`-function. The `$info` function is part…
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for (genvar ..) generate_statement() is not supported in Quartus
it likes
generate
genvar g;
for(g ...) generate_statement()
endgenerate
The suggestion is made to add ifdef QUARTUS aroun…
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I have a config that includes a single file as source but the hdl_checker log file says the file path is not built and missing simicolons etc. are not reported. Is is possible to find out what the pro…
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Author Name: **Tobias Rosenkranz**
Original Redmine Message: 3180 from https://www.veripool.org
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Hello everyone,
I have a problem with enumerated type methods. I always get an
```
Signa…
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Due to the support for verilog language of current version is poor. Please add the official support for verilog HDL and Systemverilog language.
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Following the vivado example provided for vhdl (found at vunit/examples/vhdl/vivado), I run:
`python generate_vivado_project.py`
which launches vivado, runs without error and exits vivado. Then …
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Hi!
Could you clarify, please, what part of SystemVerilog is supported by VUnit or where I can check it?
My company uses SystemVerilog and we worry what we cannot use VUnit because of it.
Best …
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UVM testbenches are widely used for verification, and Vunit could be used as a flow-controller for such methodologies, if some adaptations are made.
UVM testbenches have a top-level SystemVerilog m…
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Hi there! Thanks for making this awesome tool. I see integration with Syntastic is possible, but what about [ale](https://github.com/w0rp/ale)? Is this currently possible?