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Hi,
I am using Force() function to force internal signals. But I found it has no effect.
Force() does work for those input signals without HDL drive.
Since force function in systemverilog can for…
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I'm working on finalizing another generator for [ROHD](https://github.com/intel/rohd) that uses [CIRCT](https://circt.llvm.org/) instead of the native ROHD SystemVerilog generator. I've used both gen…
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```
ERROR: [XSIM 43-3225] Cannot find design unit topEntity.testBench in library work located at xsim.dir/work.
```
It seems to try to simulate `topEntity.testBench` instead of `testBench.testBen…
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Since SpinalHDL seems very similar to Chisel, I think it would be useful to provide a detailed comparison. The only thing I can find is an archived [Reddit thread](https://www.reddit.com/r/chisel/comm…
mtvec updated
2 years ago
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Merely including `mem.first()` (not executed though) leads to wrong simulation results. If I include `mem.first()`, then the combinational path is evaluated twice, otherwise only once. Here is an exce…
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I have been using icecream + ccache to speed up builds of the C++ output by Verilator. This works to some extent when running with -Oi to disable module inlining in order to give ccache a chance. The …
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Error is thrown on files wen tried to execute analyze in design vision
Example of error is as below.
```
Compiling source file /home/prasar00/project/pulpino/rtl/components/sp_ram.sv
Error: /…
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## Describe the bug
The incoming signal behaves incorrectly in a certain case. Adding a useless assignment operator solves the problem.
## To Reproduce
Steps to reproduce the behavior:
1. [Get p…
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It seems I can write something like `m.d.comb += Assert(Past(signal) == 0)`. If `multiclock` is off in the sby file, what exactly is `Past`?
Here's an example. First, `example.py`:
```python
f…
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@go2sh hello,
could you please check how many python3 threads can open? if i run with -p 30, total 2000 testcases, i found the simulation is hang. not the testcase issue, if i sim the testcase alon…