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It seems or1k has an timer object built into the CPU core?
litex has its own timer object.
Figure out the following;
- [X] If the inbuilt or1k timer object is available on real litex SoCs? -- **…
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I don't seen any import in code.
Is this dependency really needed on all platform? Installation on windows seems difficult...
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On my machine, the command `./kosagi_fomu.py --cpu-type None --build` gives
```
INFO:iCE40PLL:Creating iCE40PLL, SB_PLL40_CORE primitive.
INFO:iCE40PLL:Registering Single Ended ClkIn of 48.00MHz.
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Hello author, I read your paper on DAG, which is a very excellent research. I would like to ask about the experiment of using DRAM with DPU-v2. Since the crossbar (64 x 64 x 32) is difficult to implem…
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There are many issues being caused by the lack of virtual addressing.
This issues specifically involve I/O memory mapping for GPIO/Ethernet etc. and also System memory mapping for Virtualisation.
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Currently, this repo provides a custom systemd service and script (in `examples/passthrough/linux/systemd/`) to load our custom AD1939 and TPA613A2 drivers. This is perfectly functional, but systemd a…
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Sometimes when starting Jackd channel 1 becomes channel 7, sound moves form the fisrt rca jack to the seventh one. This occurs roughly 1 time out of 10. Restarting Jackd returns channel 1 to rca 1.
I…
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Hi Olof,
I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires driven?
Thanks in advanc…
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Hi,
I am trying to build rocket chip for terasic de2115. There are some issues which i think some one with more knowledge on rocket support for de2115 could clarify more and suggest fixes.
I fi…
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Correspondence from RIFFA Users Mailing list:
In riffa_driver.c, can you find the method declaration for __udivdi3, and change the method header as seen below:
Currently:
unsigned long long __udiv…