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Current definition using the python dsl is annoying. Define a hdl inspired language and parse it into our current datastructure.
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I have from Kicad a simple voltage divider, Divisor.cir: https://ctrlv.it/id/45314/1698504025
I want to read it and simulate in Pyspice using the following code https://ctrlv.it/python/45312/23883260…
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I have implemented a demo for XML system components. Components could be divided into two big groups:
* Static components: usual active and passive devices. Branch number and appearance always is …
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I am trying to describe a cmos `not gate` in a netlist but every time i call the subcircuit the output seems not to be correct e.g.
```
* supply voltages
Vs Vss 0 type=vdc vdc=0
Vd Vdd 0 type=vd…
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Author Name: **Leon Medpum**
Original Redmine Issue: 1205 from https://www.veripool.org
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Git version: 5f176d451876f859bce9ce294a67e3874aa2dfe6
We have some verilog that looks like this…
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Hi,
first of all, I don't know how stable is the reworkDev branch supposed to be, so if the below described issue is a known problem, please close this ticket.
I tried the reworkDev branch and I lik…
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Author Name: **Shareef Jalloq**
Original Redmine Issue: 1179 from https://www.veripool.org
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Hi there,
I'm seeing an error reported when trying to parse a file that uses wildcard import…
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There may be way to overcome #34 and #41.
I started implementation of `spice4qucs` extension. This extension allows you to switch between `qucsator` simulation kernel and `ngspice` simulation kernel.…
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Spice4qucs is a feature that enables to simulate Qucs analog circuits with Ngspice and Xyce engines. See #77 and #181 discussion threads for more info. I and Mike Brinson made more than 80 commits at …
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Xyce is a new spice-compatible simulation kernel. It provides circuits simulation using parallel computations (via openMPI ). More info about Xyce at http://xyce.sandia.gov/. The purpose of QucsXyce i…