-
Hi,
this is a request for comments for a feature I need and want to implement. The goal is to being able to generate files during the FuseSoC run. I describe the proposed extensions below:
## Fi…
-
Would it be possible to get SystemVerilog support? I noticed that in the VHDL issue (#203) a repository of sample code for VHDL and SystemVerilog was supplied: https://github.com/mbgh/aes128-hdl
-
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
Info: Processing started: Tue Aug 28 06:33:51 2018
Info: Command: quartus_map --rea…
-
Colorscheme becomes black and white when file with extension .v or .sv are opened.
Note - I'm using syntax files for .v and .sv file types
-
Currently the Vivado backends (and others as well from a quick look) don't place HDL sources into the project file in the order they are resolved from the dependency resolver, but reorder the files. T…
-
Hi, I am trying to run with IES 15.20 but am not able to make due to an ELF header error.
I am using python 3.5.2 on CentOS. Our system has multiple python versions installed and we specify the ver…
-
Hi,
I am studying OPAE with BBB from examples available here https://github.com/OPAE/intel-fpga-bbb/tree/master/samples/tutorial. According to these examples I can see that CCI-P protocol between the…
-
My part of run.py code:
```python
vdfb_tb = lib.test_bench("vdfb_tb")
vdfb_tb.add_config(post_check=check.post_check(output_path))
vu.main()
```
Problem: my post check function have launched bef…
-
I didn't expect it from NVIDIA. Last Verilog standard -- 2005 (Verilog-2001 is probably the last standard widely used). Merge of SystemVerilog and Verilog standards -- 2009 (8 years ago, it's about 4 …
elegz updated
6 years ago
-
Hello,
Can you please add support for the [SystemVerilog lexer][1]?
- **hdl** lexer [source][2]
[1]: http://pygments.org/docs/lexers/#pygments.lexers.hdl.SystemVerilogLexer
[2]: https://bit…