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The SkyWater PDK documentation should include a full example of how to create a RISC-V SoC design using the [OpenROAD ASIC tool flow](https://theopenroadproject.org/).
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Hi,
I know it is a little bit early at the moment, but here are my Whishlist items:
- SSB Support this is AFAIK an SDR so why not doing SSB
- A better switch of the primary channel, at the moment I …
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A number of people have expressed a desire to use nMigen for ASIC design. This issue tracks missing aspects of that workflow.
- [x] On FPGAs, asynchronous resets inhibit inference of BRAMs, DSPs, …
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### Description
Providing a nonexistent clock (should be wb_clk) in user_project_wrapper:
```
wb_buttons_leds wb_buttons_leds ( …
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For FPGA, there's a host and a device code. The programmers can write HeteroFlow code in the following style:
```python
target = hcl.platform.aws_f1
s = hcl.create_schedule([in_list], kernel)
s.to…
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While I was trying to learn this repository :
_https://github.com/nalevihtkas/EDA-tools-in-ASIC-Design-flow_
I noticed that there is no corresponding input example.
Do you have an example of …
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Would be nice to define version of verilog to output.
I not mean version 1995, but as I can in README by default using SV syntax.
Unfortunately, in 2020y some people or even Co still using pure ver…
iDoka updated
4 years ago
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### Description
This is a bucket-issue for improving Questa support in OpenTitan.
> I want to use this issue to drive support forwards by gathering user feedback into a working branch of fixes, …
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I am not sure if my understanding is correct.
I have checked the data in the gzip.inbound, and the head data are
0x400000000a000400 SoT 0xff
0x0000000000000000 EoT 0xff
0x800000000a00…
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Awesome list! Many thanks for keeping it up-to-date!
Here are a couple more:
eSilicon
https://www.design-reuse.com/news/42671/esilicon-deep-learning-asic.html
ST Micro
http://www.eenewseurope…
bfbca updated
6 years ago