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Otherwise with a well designed ASIC it can be more efficient to regen the palette for each iteration than reading of off the memory (in theory at least). Currently palette generation takes 400ms and w…
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Two categories of possible errors have been checked at the time the mapping Excel docs were finalized:
- **Errors due to pin-assigning in the process of mapping each net/connection:**
1. Check tha…
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### Description
Providing a nonexistent clock (should be wb_clk) in user_project_wrapper:
```
wb_buttons_leds wb_buttons_leds ( …
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For FPGA, there's a host and a device code. The programmers can write HeteroFlow code in the following style:
```python
target = hcl.platform.aws_f1
s = hcl.create_schedule([in_list], kernel)
s.to…
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- As we consider SRAM22 for an asic design: Was SRAM22 already taped-out in SKY130 before?
- Would it be possible for external users, who have access to corresponding licenses (or open source tools…
c-93 updated
6 months ago
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A number of people have expressed a desire to use nMigen for ASIC design. This issue tracks missing aspects of that workflow.
- [x] On FPGAs, asynchronous resets inhibit inference of BRAMs, DSPs, …
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Would be nice to define version of verilog to output.
I not mean version 1995, but as I can in README by default using SV syntax.
Unfortunately, in 2020y some people or even Co still using pure ver…
iDoka updated
4 years ago
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While I was trying to learn this repository :
_https://github.com/nalevihtkas/EDA-tools-in-ASIC-Design-flow_
I noticed that there is no corresponding input example.
Do you have an example of …
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### Is there an existing issue for this?
- [X] I have searched the existing issues
### Current behaviour
I encountered an error when attempting to use the estimatesmartfee method.
But node only re…
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The SkyWater PDK documentation should include a full example of how to create a RISC-V SoC design using the [OpenROAD ASIC tool flow](https://theopenroadproject.org/).