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Using the latest release of sv2v, I get Parse error: missing expected `end on this code:
```
function automatic logic [7:0] clz(logic [15:0] op);
logic [7:0] count = 16;
begin: loop
for (int…
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OS : MacOS 14.3.1
IDE : VScode
Simulator : Iverilog
我准备使用Digital-IDE对自己的设计进行一键仿真。在我将HDL代码通过软链接到`/user/src`后,出现了报错
报错如下:
```
Errors happen when parsing /Users/chenyulong/Desktop/npc/veri-sim/test…
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Although iVerilog supports the -f command, it does not support another popular command: -F. The -F command processes the list of files in the indicated files relative to its folder. For instance:
-…
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Hi guys,
I am currently trying to have the graphic linter of iverilog using a remote SSH connection to a virtual desktop containing those files.
The SSH connetion is established using "Remote - SSH"…
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Hi @manucorporat , The linter-verilog on my Mac could only distinguish "syntax error" without indicating what it is that cause the error as your screenshot on the setting page of linter-verilog.
I c…
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The DFF has 0 initial value assign as shown below:
![ddd](https://github.com/steveicarus/iverilog/assets/92973755/1ff91065-ef20-4a3c-a407-46150cbe4aca)
When simulation is run on iverilog vs VCS th…
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Xilinx (and probably iverilog) issue warnings if a variable is used before it's declared.
It doesn't appear to be a functional issue, but best to not have such warnings.
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I've been trying iverilog ("icarus verilog") on the system verilog code output from clash (approx 1.6.3) but it won't compile, well, parse, because .... iverilog doesn't seem to accept the repeat …
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verilog file generated(with `:verilog` in clashi) from below source fail to compile with iverilog.
``` haskell
{-# language FlexibleInstances #-}
module Test where
import Clash.Prelude
import…
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