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openXC7 0.7.0 update (more specifically yosys) introduces a build regression for litex-ddr-kc705 and litex-ddr-hpcstore-k420t demos due to unsupported inference of RAM128X1S/RAM256X1S (LUTRAM/Distribu…
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Hi IPBus team,
I have a problem following the instructions reported at:
https://ipbus.web.cern.ch/doc/user/html/firmware/exampleDesigns.html#build-instructions
using as board the **kcu105** mod…
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Hi
I konw it depends on the midas, But i don't konw how to add it, Can you give me some solustions?
Thanks!
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Dear Garankonic:
I am now facing some problems of using 88E1111. My borad uses Xilinx Artix-7 and MGTP pin is connected to the PHY chip. Now I have to use GTP core to connect several FPGA bo…
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Hi,
I adapted your code to run on the KC705 at 10Gbps.
I tested ping, echo server, PC to FPGA custom data transfer and it work fine so far.
I have however an issue when the FPGA send the data…
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Hi
The Adept version recommended by the documents are too old to be able to download from the
https://reference.digilentinc.com/software/adept/start
Is it workable to use the newer version to r…
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I try to port to VU440 but fail to make the project. My steps is as below. Please provide some advice. Thx.
1. Copy from project VCU108/fpga_1g to VU440/fpga_1g/
2. Type make to build the original…
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manish@manish:~/Desktop/Connectal/connectal/examples/echo$ make run.kc705g2
grep: /home/manish/Desktop/Connectal/connectal/boardinfo/.json: No such file or directory
make -C kc705g2 --no-print-direc…
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Can you add the script/command used to generate the litex builds? I can't my own builds to work with the toolchain.
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The sustained DMA event rate is surprisingly low on Kasli. Using the below experiment, I find that shortest pulse-delay time without underflow for a TTL output is:
* Opticlock: 530mu
* DRTIO local T…