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After running [BUFGMUX example](https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1419) on [Nexys Video with limited grid](https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1505) I obtained th…
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Hi,
I am a starter in this code and would like to initially change some Naxriscv instructions.
To provide some context, I was able to successfully compile and run litex, flash the board, and e…
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Hi,
I have implemented **Rocket64b1gem16** on my FPGA with **default configs** and **8GiB DDR3**.
The ONNX Resnet18 Model sometimes can run with command '-O 99' and I can get the right result. But s…
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## Problem statement
Currently, the number of IDELAYCTRLs in a design is fixed to the number of instantiations in the design itself.
It is common though, that there are multiple IDELAY banks tha…
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When USE_CLK90 == "TRUE", phy_rgmii_tx_clk register has very tight timing on the data path: clk90 - clk = 2ns. Vivado often fails to meet this timing on Artix-7 FPGA.
I made few changes rgmii_phy_i…
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Hi All!
I'm trying to integrate the L2 InclusiveCache from ChipsAlliance (https://github.com/chipsalliance/rocket-chip-inclusive-cache) with a single Rocket core to be used inside the Litex SoC.
…
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I think it's a great idea to split the buildenv from the firmwares.
The problem now, though, is that I have to have files in the platform, target, and firmware directories specific to a given appl…
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To reduce the amount of code duplication we should subclass from `litex` platforms' `_io`, `connectors` and methods instead of redefining them. This will prevent surprises and subtle incompatibilities…
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_From @mithro on July 17, 2014 6:27_
Something like memcheck or similar.
Performance things to check;
- Write a large contiguous block.
- Read a large contiguous block.
- Write at random locations.…
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the issue metioned on:
https://github.com/litex-hub/linux-on-litex-rocket/issues/40#issue-2324887509
i found the arty.dts had a node with interrupts-extended:
```
L1: interrupt-controller@c0000…