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https://riscv.org/about/
https://en.wikipedia.org/wiki/RISC-V
**Description:**
RISC-V is a relatively new open standard instruction set architecture (ISA). With only 40 base instructions it is …
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Some new paths in function `createNewDirForFile` from `Paths.h`. Can be unavailable.
Example:
file = /home/utbot/.opam/4.08.0/share/sail/lib/sail.c
oldBase = /home/utbot/sail-riscv/c_emulator/SoftF…
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Currently Sail can generate a C simulator (using the `-c` option) and an OCaml one (using `-ocaml`). The latter is much slower. Keeping them in sync occasionally causes problems, in particular in the …
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### Description
I think there is a bug in Virtqueue implementation:
https://github.com/renode/renode-infrastructure/blob/b83aa9b46e518171f6c061cfe4fd6a5cfa5c734e/src/Emulator/Main/Storage/VirtIO…
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in src/cpu.c ( lines 609-614 ) we have :
```
case ADDSUB:
switch (funct7) {
case ADD: exec_ADD(cpu, inst);
case SUB: exec_ADD(c…
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I modified the file rocket-chip/src/main/scala/system/Configs.scala
I've added a line: `class MyConfig extends Config(new WithJtagDTM ++ new DefaultConfig)`
Then i launch in rocket-chip/emulator `ma…
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When I change CoreMark for RISCV(spike or Rocketchip), I also find gettime() always return 0 (start_time() and stop_time() always return -1) . I think it may some problems of clock in emulator. Could …
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The current emulator code has been written with Win64 in mind however current testing is being performed on macOS, Linux and FreeBSD. There are some sections of code that need to be abstracted.
The P…
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Hi guys. I really love your project and it's awesome.
Currently I'm trying to run NodeJS in libriscv emulator.
Here is my fork with changed configs https://github.com/emcifuntik/unofficial-builds/…
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Hi!
I have a question about compiling programs for 32-bit cores. I tried to use Verilator to test Bare Metal RISC-V Programs with TinyCore( Is it 32-bit core, right?). First of all, I make TinyRoc…