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Hello,
We have tried to implement RV32M extension instruction, please have a look. The extension instruction also passes riscv-test benchmark. If you want your riscv-atom to support RV32M, you can l…
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The 32bits compiler (riscv-gnu-toolchain) is configured with ```--with-arch=rv32gc --with-abi=ilp32d```.
PK is configured with ```--host=riscv32-unknown-elf```.
And I have alreay added rv32gc_co…
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This seems to happen in some gcc tests. The current draft of the zfinx reserves passing double arguments in odd offset register pairs.
Here are some tests I saw failing:
```
FAIL: gcc.c-torture/e…
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Why instruction encodings of rev8 and zext.h are different in RV32 and RV64? But, other instructions that both belong to RV32 and RV64 don't have this characteristic, for example andn and clmul.
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Currently, the SBI PMU spec[1] defines the raw event type as follows:
> On RISC-V platform with 64 bits wide mhpmeventX CSRs, the event_data configuration (or parameter) should have the 48-bit valu…
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the make process is finished, and make run-emulator error shown as follow:
```
hessen@ParaComp:~/risc-v/riscv-sodor$ make run-emulator
running basedir/Makefile: make run-emulator
make -C emula…
hz0ne updated
5 months ago
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reported by Hugues
$ python3 -m asmde.asm_stats --arch rv32 --input examples/riscv/test_rv32_f.S
parsing input program examples/riscv/test_rv32_f.S
unable to parse [Lexem(fadd), OperatorLexem(.), L…
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'mem_read_priv()' [riscv_mem.sail, L180] declares the address argument as 'xlenbits'
But Sv32 phys mem addrs are 34 bits, not 32 (XLEN) bits.
If RV32 is configured WITHOUT Sv32, are phys addrs 3…
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When I run make reports after 'make run-emulator' I get errors like these grep CPI emulator/rv32_1stage/output/_.out
make: [rv32_1stage-report-cpi] Error 1 (ignored)
and test-results.xml is all 0
$ ma…
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In https://github.com/Mi-V-Soft-RISC-V/miv-rv32-bare-metal-examples/tree/main/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky there is a link to https://github.com/Mi-V-Soft-RISC-V/miv-rv32-docu…