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There is a sample :
command :
riscv32-zephyr-elf/riscv32-zephyr-elf-gcc **-march=RV32I** -fno-inline -fno-common -DTIME -DCORE_HZ=12000000ll -I/home/spinalvm/hdl/tools/zephyr-sdk/sysroots/riscv3…
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wally32priv and wally64priv are timing out during nightly regression.
regression-wally --nightly
However,
wsim rv32gc wally32priv
runs without error
regression-wally
also runs without err…
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I am using the following command to generate arithmetic tests for `rv32i` target
```shell
python3 run.py --target rv32i -o $HOME/temporary/riscv-dv -tn riscv_arithmetic_basic_test -i 10 -si pyflow…
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This concerns the SLLI encoding. From the spec, the rv32i SLLI instruction is encoded as follows:
![slli-32](https://user-images.githubusercontent.com/10012248/62536877-035b1380-b847-11e9-92d3-d5aa…
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make[1]: Entering directory `/fac/proj/xxx/imperas-riscv-tests/imperas-riscv-tests'
make -j8 --max-load=4 \
RISCV_TARGET=riscvOVPsim \
RISCV_DEVICE=rv32i \
RISCV_PREFIX=/project/usr-xxx-RHEL…
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When running the `riscof coverage` command, warning are emitted as errors.
```shell
> riscof coverage --cgf-file riscv-arch-test/coverage/rvi.cgf --config=config.ini --suite riscv-arch-test/riscv-te…
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According to https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf the SLLI, SRAI and SRLI instructions are part of RV32I. Here they are only included in RV64I.
I can make a PR for this …
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Using the following commands:
```
riscv64-unknown-elf-gcc -nostdlib -nostartfiles -Tlink.ld -m32 -o inst inst.s
spike --isa=RV32I -d inst
```
and then inside spike any of these:
```
pc 0
reg 0
mem …
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Some instructions have different encodings between RV32 and RV64.
From the RISC-V ISA Specification (20191213), Chapter 24, "RV32I Base Instruction Set":
![image](https://github.com/ThinkOpenly/sa…
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Hi Stephan,
your [Prebuilt GCC](https://github.com/stnolting/riscv-gcc-prebuilt) is a real big deal. It makes the compile of source code easily. But whenever you are in need to build your GCC from …