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**Right now we have the following checks:**
These checks are meant to check a certain function in SpyDrNet-TMR:
* **drc_apply_nmr** - meant to be run right after calling apply_nmr() to see if what…
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As far as I am aware, the only way to get a netlist out of modern Quartus is using the EDA Netlist Writer feature, which outputs a Verilog post-synthesis netlist, designed for simulation with timing. …
agg23 updated
10 months ago
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Unable to generate a TMR netlist
ValueError: Applying name would result in a naming conflict
namespace_manager -> init.py
Line 107 - if parent and parent in self.namespaces:
possible fix - if …
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In order to be able to orchestrate generation from other python codebase (or jupyter notebooks) it would be nice if OpenFASOC exposed a python interface over the main generators flows that can be `imp…
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A user of the documentation suggested the following improvements
* The documentation is too FPGA specific and it should be expanded out to include asic designer and others
* It is not clear how …
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There are several branches that are "stale". We should go through these together and try to clean it up.
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This is probably a minor issue, but right now, instance.get_pins() returns inner pins but instance.pins returns outer pins. Shouldn't they both return outer pins?
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In the current master branch, the following netlist with big-endian bundle declaration is incorrectly handled.
My understanding is then big-endian bundle is defined `is_downto=False` and pins will …
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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The netlist generated by spydrnet uses `\` and `` for constant 0 and 1, but it doesn't actually assign or drive these signals.
For example, I have the following netlist:
```verilog
module test…