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```
Could you please add support for highlighting Verilog and System-verilog ?
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Original issue reported on code.google.com by `alertj...@gmail.com` on 26 Sep 2013 at 2:54
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Hello,
I am looking for up-to-date complete System Verilog grammar.
I know about:
* full std 2012 (but still not perfect and tested) https://github.com/Nic30/hdlConvertor/blob/master/grammars/…
Nic30 updated
4 years ago
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### Before start
- [X] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual). 我已经阅读过 RISC-V 指令集手册。
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readth…
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The unit should contain the pinout diagram , block digram , rtl code in system verilog with parameterize signals and add the proper documentation of the unit and also explain the jargons realted to u…
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Type of issue: feature request
Impact: unknown
Does Chisel compiler or FIRRTL support the conversion or the compilation to System Verilog besides Verilog?
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The unit should contain the pinout diagram , block digram , rtl code in system verilog with parameterize signals and add the proper documentation of the unit and also explain the jargons realted to u…
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Section 10.8 of the system verilog LRM covers labeled statements, and I'd like to try yosys on a project that has code using them. Here's an example of a labeled statement:
```
module test_label_pro…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything rel…
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How can use Verilog/system-Verilog testbench to verify the function of USB device?
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### What's hard to do? (limit 100 words)
Making the generated Z3 code independent and provable standalone. There are three things I would like to address:
1. The assertion node is unhandled whil…