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Cool improvements that will help development might be:
1. Allow `int` / `uint` constraints (the more complex task can be usage of Int256 in codegen and allow them as NAT)
```
a$_ a:uint32…
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I believe there is some sort of a TLB like structure used in SAIL which prevents PTW to be triggered for each memory/instruction access. It would be beneficial if we can have a switch via the cli to d…
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The file tlb needs to be created from mscorlib.dll. However there is currently no easy way to extract an TLB or IDL from it.
This is to support VS2008 express.
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When there is a page fault on a symbolic address, the address gets concretized in tlb_fill() when being written to the cr2 register.
This could probably be avoided by making the address concrete but …
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Hi,
I am trying to compile the simulator and found that tlb.h is missing.
Pankaj
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### Describe the Bug
TLB Miss on Disney's Up when entering a dark cave.
### Reproduction Steps
3rd level.
### Expected Behavior
emulator doesn't crash
### PCSX2 Revision
dev-1754
### Operati…
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When I was trying to simulate a realistic Skylake CPU using Drcachesim, I found that I can not create a TLB with 1536 entries in Drcachesim. Drcachesim only allows TLBs size to be a power of two, whic…
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**Describe the bug**
Executing `clflush` instruction in FS mode caused this assertion error,
```
src/sim/simulate.cc:199: info: Entering event queue @ 14392355269750. Starting simulation... …
hnpl updated
4 months ago
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Hi Coyote Maintainers:
I am a PhD student from Northeastern University in Boston, US. I am considering using Coyote RDMA part in our project to communicate with Mellanox RDMA NIC. I am currently tr…
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It would be useful if in some mode (perhaps we can abuse `-t` for this?) MSIM would warn about possibly wrong use of TLB.
* Set `TS` field (TLB shutdown) in `DS` (diagnostic status) of `status` reg…