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**Is your feature request related to a problem? Please describe.**
A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
**Describe the solution you'd like**…
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Check whether or not following tools support generated CSR modules/RAL packages.
* Simulation
* Cadence Xcelium
* VHDL output
* Mentor Questa/ModelSim
* Aldec Riviera-PRO
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when I opened model_sample.slx, used embeded coder in simulink which used ert_linux.tlc, after clicking generate code, there is error as following. please let me know anything I missed.
Thanks/Fo…
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For users who have license for these because they purchased an fpga from the vendor, and don't necessarily have access to vcs
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Hello,
I am trying to simulate a larger top level design (entire Series-7 FPGA), featuring several transceiver-based IPs. So far, I have been able to simulate this design when not using VUnit (just…
anro7 updated
3 years ago
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Xilinx's Vivado simulator supports DPI, though it doesn't seem to support VPI. The flow seems to be just like the Icarus VPI flow, with the `xsc` tool used to compile the library like `iverilog-vpi` a…
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### Is there an existing issue for this?
- [X] I have searched the existing issues
### Describe the bug
Input `pre` is not used in the Verilog code for `DflipFlop`.
```verilog
module Dfli…
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I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not know what is goi…
jeras updated
2 years ago
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## Observed Behavior
When I try to simulate the Arty A7-35 example in Vivado, I get an error message in elaborate.log:
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/top_art…
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I wanted to simulate the core to view wave forms of different instructions. But i am struck. I am getting this error "FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from …