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Hi Olof,
Thanks for creating serv.
It's the smallest RISC-V CPU I could find so far.
Small enough that it almost fits on the Speed Tang Nano. (It's just off by 100 or so LUTs.)
I saw that you post…
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Hi @farzadfch.
I read your paper 'Integrating NVIDIA Deep Learning Accelerator(NVDLA) with RISC-V SoC on FireSim'.
In your paper, you change the LLC size.
Now, I have two questions.
(i)Could you t…
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Generation of bit stream.
` litex-boards/litex_boards/targets/xilinx_ac701.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet`
--> Bitstream generated successfully…
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Hello,
I am currently trying to generate linux image to simulate linux booting on VexRiscv.
To do so, I follows guidelines in src/main/scala/vexriscv/demo/Linux.scala:
```
Buildroot =>
git cl…
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Hi guys,
I've been looking here and there of instructions/info if there a a latest image (like RCN's generated images) available, or concise instructions on how to use theDe0-nano-soc with the mesa n…
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Following the guide:https://github.com/pulp-platform/pulpissimo/blob/master/rtl/tb/README.md, I tried the OpenOCD to connect the RTL platform and get the errors below.
on RTL platform side, continuou…
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Hello all,
I'm having a little problem with the FPGA implementation to test functionality on sillicon and the compilation is completely fine but when it comes to interfacing with the board.
The Open…
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I'm sure this has been discussed, but I thought I'd write down my thoughts on a top-level driver.
Today there's a number of siloed tools that have been stitched together with the alpha-release/flow…
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Hi, as you know DE10 pro FPGA is very costly board. I have a PYNQ-Z2 FPGA board (board details are here https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html). I want to do some research on SIMTight. …
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Hello,
I'm playing with colorlight 5A75B board, with a etherbone client on it.
Now it's connected directly to pc ethernet port trough phy1 connector.
Would it be possible to daisy chain another sim…