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**Submitting author:** @suneeshjacob (Akkarapakam Suneesh Jacob)
**Repository:** https://github.com/suneeshjacob/ACRoD
**Branch with paper.md** (empty if default branch):
**Version:** v1.1.4
**Editor…
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EL2 Memory interface
Top-Level el2_mem_export interface is not defined with modport direction. No concern for simulation, but synthesis flows require direction declaration.
Recommendation is to driv…
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## :question: General Issue
### The Question
Is it possible to do asynchronous processing in a Construct? Is there anything in CDK that will wait for a promise to resolve? It seems that everything…
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貼吧活動:(請查閱 [SARS-CoV-2 Timeline by 2020.02.21](https://github.com/agorahub/_meta/blob/agoran/theagora/sari/Memorandum_2020-02-21_SARS-CoV-2-Timeline_Nathan.pdf?raw=true), by Nathan :cloud: )
- Colla…
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Hi @Dolu1990,
First and foremost, congratulations on the excellent work in VexRiscv and NaxRiscv.
I've encountered an issue with the `VexRiscvAxi4LinuxPlicClint.v` file generated by VexRiscv. It…
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This is a tracking issue which should not be closed until all known circuit issues have been resolved.
Known issues:
- [x] `(fib 100)` proofs fail to verify. [verified fixed in #113]
- [x] `test_…
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## What do you want to change?
Clarify the Boot vs NKRO functionality and implementation. This is mostly me thinking out loud and trying to capture a few things before possibly suggesting some more…
tlyu updated
10 months ago
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### 模块 / Components
- [X] venus-sector-manager
- [ ] venus-worker
- [ ] 工具链 / toolchains
- [ ] 文档 / docs
### 版本 / Version
```text
venus-sector-manager version v0.6.4-prod-git.3df9313
```
### 描述 /…
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## Announcements - New Features, Design Patterns, and Methods
I'm unsure how GitHub sends out updates. I don't think people are informed about Wiki changes for example. I've been announcing new f…
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Putting the following example in the flow SV --> UHDM (w Surelog) --> Yosys (w f4pga plugin) --> SV shows that the following verilog with bit direction is incorrect:
Input:
```systemverilog
modul…