-
I'm very new to FPGA designs and the litex tools and I'm sure I'm missing something obvious, sorry if this is the wrong place to post this.
I'm trying to build a Vexriscv CPU on an Arty A7 with tri…
-
Would it be possible to add a `--quiet` option switch so that openFPGALoader does neither emit:
- `=` progression chars on stderr
- completion %-age on stdout
This would be very useful to use it …
eblot updated
3 years ago
-
With the availability of the artix 100T device, we can enable tests on the arty a7 board as well.
This translates into:
- adding the arty_a7-100T board specification
- adding constraint files to …
-
**Description**
In releases after [zephyr-v2.1.0](https://github.com/zephyrproject-rtos/zephyr/releases/tag/zephyr-v2.1.0) the shell module no longer accepts input on LiteX/VexRiscv running on an Art…
-
Sadly almost nothing to include with the report, left the current April 19th Fedora image, kernel 5.10.6+ running overnight.
System apparently wandered off and just stopped responding, dropped netw…
-
Many public XDC files provide `get_ports` arguments in curly brackets:
https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-35-Master.xdc#L7
Currently, support for this feature is missing …
-
@litghost were very persisten that I should create an issue about this one in this repo, so here it is.
The error in short is:
```
FileNotFoundError: [Errno 2] No such file or directory: '/home/…
-
I was using the EtherBone host bridge to transfer large amount of data between PC and Arty A7 with 100Mbit Ethernet and experienced some performance issues. While write performance is sensible, read p…
-
It would be good if the examples also worked on the Arty 100T version.
-
I've been working on getting some circuits running on an Arty-A7 board and think I've ran into a bug in the HDL generation.
When I try to generate the HDL, I get a pretty generic error: 'Error duri…