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https://github.com/timvideos/litex-buildenv/wiki/Bootstrap
```
juser@cnt5:~/h2u$ curl -fsS https://raw.githubusercontent.com/timvideos/litex-buildenv/master/scripts/bootstrap.sh | bash
Cloning …
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Hi Clifford,
first thank you for this project, seems a really good way to handle new open source designs as the community grows!. So, I'm trying to get started with it inserting the RVFI in my core b…
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I found that I cannot call some of my functions properly. In order to build an Arduino like structure I use the functions `void setup(void)` and `void loop(void)` and call them from the `main` functio…
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[VexRISCV uses]()
` variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")`
[picorv32 uses;]()
` variant == "minimal":`
[mor1kx uses](https://github.com/enjoy-…
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## Steps to reproduce the issue
On 64947453: `valgrind --leak-check=full ./yosys picorv32.v`
## Expected behavior
No leak.
## Actual behavior
Allocation in question: https://github.com/…
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I'm considering updating the picorv32 core for the FuseSoC standard library, but it would be great to have a tagged release that I can use
olofk updated
5 years ago
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Hello Cliff,
Any chance that you will be implementing a jtag interface?
Thank you,
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Hi,
Does not work with the latest Litex
many errors like:
/usr/local/lib/python3.7/dist-packages/litex-0.2.dev0-py3.7.egg/litex/soc/software/include/base/irq.h:46:2: error: #error Unsupported …
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Hello,
I tried synthesizing the PicoRV32I core in design compiler using 250 nm LEDA library and got a gate equivalent of 5437 (number of cells in DC area report). I am just wondering if the gate c…