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### Project Name
DRV64IMZicsr
### Description
DCD’s RV64IMZicsr RISC-V Core
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support. As a part of the DRVX Core …
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I want to add a new slave peripheral to Riscv, and I took SRAM as reference to know the modules and packages that I should modify, and I found that I should add:-
1) Index, start and end address in t…
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I would like to compile my SV code with yosys+UHDM, I followed the instructions from here:
https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/
except I…
jeras updated
2 years ago
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Dear LiteX devs.
I enjoy LiteX very much, great work great concept! Hope I can help.
### Background:
Yesterday I naively experimented a bit with Litex - platformio - zephyr(rtos). The idea was …
hvegh updated
3 years ago
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Open On-Chip Debugger 0.11.0+dev-04033-g058dfa50d (2023-02-20-09:48)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
/home/wjc/Desktop/VexRiscv_old/cpu0.y…
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I would like to simulate USB devices on the ATSAMD21, up to the point that I can hook the model up to USB/IP and use it from the host. In particular, I'm interested in simulating USB HID devices, but …
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Hey guys!
I dont have a de10soc , but i have a de1soc(board).
I would like to know if anyone has tried to implement this fantastic work in it.
Do you think it is possible to implement on the de1soc…
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Quartus Pro 20.1 claims pin clashes:
```
Info(175029): IO12LANE_X61_Y327_N2
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s))…
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We should be able to add support for [RPC DRAM](https://etronamerica.com/products/rpc-dram/) in LiteDRAM.
RPC DRAM reduces DDR3 pin count by removing all the command/address lines, data mask and CK…
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Hi @tcal-x and @mithro ,
I was trying to change certain parameters of the d-cache on the Vexriscv using the scala file ([](https://github.com/google/CFU-Playground/blob/main/soc/vexriscv/src/main/scal…