-
I am seeing an intermittent error at simulator start up when using `xcellium`
```
xrun(64): 18.03-s006: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
Loading snapshot worklib.aes_gcm_top:s…
-
I have a question about memory handling. The following SystemVerilog is interpreted by the frontend as a memory - the `$memrd`, `$memwr` and `$meminit` cells are generated:
```verilog
module ram(inp…
-
**Impact**: rtl
**Tell us about your environment:**
*Chipyard Version:* branch master, Hash: 19152d3
*OS:* Linux chipyard-vm 5.4.0-49-generic #53~18.04.1-Ubuntu SMP Mon Sep 21 14:12:39 UTC 2020…
-
I think for open source simulators to really take off in the industry they need to have mixed language (VHDL and SystemVerilog) support. I know very few projects that don't have some "IP" in VHDL eve…
-
Cocotb should have a fundamental concept of time. Currently the `Timer()` trigger is expressed in simulation time units, however the user has no knowledge of that this is.
We should query the simula…
-
Hello,
I established a testbench that instanciates the fpnew_top, and I'm trying to understand how I can control the interface to feed the input operands and get the result back.
I use the follo…
-
I have read this part of the verilog style guidelines:
Logical vs. Bitwise
Use logical constructs for logical comparisons, bit-wise for data.
Logical constructs (!, ||, &&, ==, !=) should be used…
-
**Description**
I have blocks of code inside if generate statements, each block corresponding to a specific value of a constant parameter `P` (e.g. set in the package file or from a generic).
I'm …
-
# Summary
Verilog header files (`*.vh`) included through `addResource()` annotations are not copied from `sim/generated-src/f1/DESIGN_TRIPLE/` to the `$(fpga_work_dir)` during the `replace-rtl` ste…
-
I'm working on a flow using Yosys to compile OpenTitan to an SMTlib description for a verification project (see #1550 for more context on this build flow). I got to a point where I was able to generat…