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**NOTE:** This was modified to include multiple issues of the same or relevant types
Hi,
Trying to use hdlConvertor to read in some VHDL files, I get the following errors in some of my files, fo…
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**Description**
Upon synthesizing my design, GHDL reports few design-related then a crash message
**Expected behaviour**
No crash message
**How to reproduce?**
Setup the design, from https://…
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In order to avoid missmatches between the cli (ghdl --help) and the docs at RTD, I think we should try to move the description to the sources, next to where the flags are defined. Indeed, the sources …
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```vhdl
--!\file
--!\brief This file contains the package that provides definition of interfaces of memory and processing module control
library ieee;
use ieee.std_logic_1164.all;
use IEEE.num…
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Had an issue earlier with my code. It seems that the generator doesn't work with such structures:
```vhdl
case my_signal is
when value1 | value2 =>
-- do something
-- [...]
```
Here is the log:…
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I expect this ticket to be a site of discussion. I assume more specific issues will be created as appropriate as the discussion progresses.
Do you expect hdlConverter to be able to read a simple V…
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I like the new `toVerilog` and `toVhdl` implementations based on running the Python classes through `toJson`. Just to be clear, here is my current understanding of the parser chain.
Current:
HDL…
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Pretty much every VHDL file will have "library IEEE;" near the beginning, but I get an error that conversion to a Python object isn't implemented.
[vhdl_lib_ex.tar.gz](https://github.com/Nic30/hdlC…
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I am trying to use Initial() like https://github.com/m-labs/nmigen/blob/57d95b7f95dd37e2527db7b04be9ac8f324133e2/nmigen/test/test_lib_fifo.py#L213-L217
this. I run test_lib_fifo.py to make sure it wo…
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**Describe the bug**
After an update, Verilog (`iverilog-unstable`) has compile errors.
**To Reproduce**
Steps to reproduce the behavior:
1. `NIX_PATH=nixpkgs=https://github.com/nixos/nixpkgs/…