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in the Fusesoc
we list all .c/.h files as `file_type: systemVerilogSource`
this makes xcelium gcc choke on aes_model_dpi.c
particularly it chokes on the include of cstring
 of riscv-compliance, `csrw tselect, x0` will …
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Author Name: **Greg Taylor**
Original Redmine Issue: 1397 from https://www.veripool.org
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Verilator throws an error on unsized literal constants larger than 32-bits, e.g. 'hFFFFFFFFFFFFFFF…
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Hi!
Could you clarify, please, what part of SystemVerilog is supported by VUnit or where I can check it?
My company uses SystemVerilog and we worry what we cannot use VUnit because of it.
Best …
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Good day!
Order and conditions
1. Adding new config WithJtagDTM in boom_configs.scala
`
class jtagMegaBoomConfig extends Config(new WithMegaBooms ++ new DefaultBoomConfig ++ new WithNBigCore…
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Hello,
I was debugging why my FFT plotting was crashing randomly..
```
/home/kmodi/.nimble/pkgs/ggplotnim-0.2.8/ggplotnim.nim(2780) +
/home/kmodi/.nimble/pkgs/ggplotnim-0.2.8/ggplotnim.nim(27…
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All off the benefits provided by VUnit for VHDL would apply equally well to SystemVerilog.
I would surely miss the VUnit features when working in SystemVerilog project.
There is actually not that muc…