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There is a few attempts to works with Xilinx SOCs with Hard ARM cores. I find these examples difficult to follow.
The example below is what i tried, and finally worked.
The principle is this: add …
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I was wondering, if one want to integrate BSG Manycore onto SoC, I think one can interface it through AXI? I was looking at the codes, I think one integrate through this one: https://github.com/bespo…
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This issue is intended to track progress on Phase 2 of [Calyx Meets the Real World](https://github.com/cucapra/calyx/discussions/1756). This writeup gives great overarching context and what we are wor…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Utilizing an updated AXI agent (PR #2416), a generated test timeout when randomizing th…
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Currently the read-compute-write AXI generator only creates a [single set of channels](https://github.com/calyxir/calyx/blob/main/yxi/axi-calyx/axi-generator.py#L658-L667) for the first `seq_mem` in a…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Hi,
I got a SoC project using CVA6 cores, which is running well with its default confi…
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Currently BITVIS_VIP_AXI vvc only supports master/manager interface where it acts as a master towards a slave/subordinate module.
Request is to develop a Slave/Subordinate interface where the VVC wil…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
In case of an AXI atomic transaction, the CVA6 crashes when we send the read data befor…
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Hi Alex,
Please share the pcie axi slave verilog.we have only pcie axi master verilog
thanks
V.P.Sampath
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Hi,
Will the driver for AXI HBICAP be added to this repo? If not, can someone please point to where I can find it. I'm using vitis+vivado to work with a vcu118
Thanks