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as suggested by @mithro in https://github.com/SymbiFlow/fpga-tool-perf/pull/50#issuecomment-592180396 we should generate the following reports:
```================================
Settings
======…
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## Steps to reproduce the issue
Build the microwatt soc. It is a mixed language implementation (vhdl and verilog), so you need ghdl and the ghdl plugin.
```
git clone http://github.com/antonbla…
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Hello, I've been studying what you've posted and I'm a student just starting to learn about the FPGA. When I follow the steps in the README, I encountered a problem with the I/O in the picture, if you…
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Sorry, if this is an offtopic, i'll move it to maillist if it's so. This is just common suggestions about "full metal runtime.js/nodejs" related to this #42 and this #43 issues.
Besides all feature…
danxn updated
9 years ago
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Hi.
First, compliments on such a well structured and documented tutorial.
I have followed it exactly as given, built linux, SD card and the FPGA examples, and the blink example works fine.
But when…
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Hello,
I am currently working with the "PolarFire SoC FPGA Icicle Kit". I have configured/flashed the device with the "Reference Design". Then, I have created an example test code (Simple LED Blin…
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Hello,
In CycloneVSoC-examples/FPGA-hardware/DE1-SoC/FPGA_DMA/ghrd_top.v, line 335:
.axi_signals_aruser (pio_controlled_axi_signals[ARPROT_BASE+: ARPROT_SIZE]),
.axi_signals_…
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It looks like it should be possible to get TinyGo running on an FPGA softcore without too much trouble.
I was reading this article earlier that describes using linker scripts for the HiFive1 and star…
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https://github.com/zylinux/computerV8
May I make friend with you.
I love computer stuff too . FPGA cpu soc etc
would you mind go give me your email or wechat ?
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Hi,
I found out a few things about ["modified" Briey SoC](https://github.com/jmio/ECP5_Brieysoc/tree/dev) not working on the actual device (ECP5, ICESugarPro).
For "non-booting" FPGAs with dev-…