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Hello. Not sure if the right place to ask, but here I go:
been trying to flash a rust program to my ecp5 fpga (colorlight 5a-75e). however when booting, im not getting the expected output.
```rs
…
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I see a few closed issues on this topic indicating that DDR in Zynq (Pynq-Z2) cannot be used because it is not accessible from PL.
When I look at the Zynq7 block design I see 4 AXI 32/64b ports from …
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See https://github.com/im-tomu/fomu-workshop/pull/410/checks?check_run_id=1616270863#step:10:5267. `add_dfu_suffix` has been removed from the latest litex_boards.
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### Version
Yosys 0.42+12 (git sha1 62bff3a20, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
try to synthesize the output of litex
…
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Hi. Trying to simulate my rust binary with:
```
riscv64-elf-objcopy mybin -O binary mybin.bin
litex_sim --output-dir=target/litex_sim --cpu-variant=minimal --rom-init=mybin.bin
```
however, whe…
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Running `flow.tcl` on `user_project_wrapper` with the default `user_proj_example` (counter) result in the following error:
```
LVS reports:
net count difference = 0
device count difference…
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Looking at typical cosmetic changes @enjoy-digital makes on top of my commits I'm wondering if there is a description of the LiteX/Migen coding style or one should be written. I normally use PEP8 styl…
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RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…
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Can you add the script/command used to generate the litex builds? I can't my own builds to work with the toolchain.