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Context:
- In October I created a ticket to discuss an add-in architecture for ARTIQ gateware #147.
- This was discussed on the mailing list on [11/13/2015](https://www.mail-archive.com/artiq@lists.m-…
ghost updated
7 years ago
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We are starting to get sphinx compatible documentation in some of our modules. It would be good to get documentation generation working and producing good results.
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Is it possible to perform cycle accurate simulation using the inbuilt simulator in migen?
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This case doesn't seem to be described in the manual. It looks like `write_verilog` completely ignores `\EN` for anything other than non-transparent synchronous ports. Migen uses "latch address" for t…
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Hello! I would like to know what is the status of the project. I want to use it but with PYNQ board. Do you have any documentation about how to use migen and vivado to make the hardware wrapper?
T…
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Cat() not behaving as i expect when i use slices ... Cat_object[slice] ...
Have tried a number of permutations ... assigning to a slice ... Cat_object[n].eq(rhs) or from a slice ... lhs.eq(Cat_obje…
scted updated
3 years ago
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My understanding is that asserting `csr.we` should cause the storage to get the contents from `csr.dat_w`. This doesn't seem to be happening during simulation.
I also found the following;
https://…
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I would like to split the build process of a design on two hosts:
- the first host would call `platform.build(run=False)` and create a build folder with the files required for a build
- that folder …
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VHDL is poorly supported by the open source toolchains. Verilog is much better supported.
It would be really awesome if this core was in Verilog instead of VHDL :-P
Then lots of the DisplayPort …
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Dual-port block RAMs in some FPGAs can have ports with different sizes. This feature cannot currently be used with Migen.