-
@bunnie has been working with LiteX / Migen recently and mentioned he thought following issue would be a big source of bugs in LiteX / Migen designs. I would like to get @sbourdeauducq 's (and others)…
-
Hi, I wonder what is the clock frequency you used during the sampling process.
Regards.
-
Hi!
We are working on getting the panologic-g2 into the [`timvideos/litex-buildenv`](https://github.com/timvideos/litex-buildenv/pull/223) repository and [`litex-hub/linux-on-litex-vexriscv`](https…
-
The current `setup.py` does not list any dependencies but litex-boards does depend on migen, litex and a bunch of litex modules.
-
Consider this minimal example:
```python
from migen import *
from migen.fhdl import verilog
class my_module(Module):
def __init__(self):
self.input = Signal(8)
self.outp…
-
Cat() not behaving as i expect when i use slices ... Cat_object[slice] ...
Have tried a number of permutations ... assigning to a slice ... Cat_object[n].eq(rhs) or from a slice ... lhs.eq(Cat_obje…
scted updated
3 years ago
-
Dear charles,
How you recommend me to compile the updated code with
```
sbt "runMain naxriscv.Gen64"
```
like which branch to stay in spinal HDL and which branch to stay in main one ?
…
-
Hello! I would like to know what is the status of the project. I want to use it but with PYNQ board. Do you have any documentation about how to use migen and vivado to make the hardware wrapper?
T…
-
Is it possible to perform cycle accurate simulation using the inbuilt simulator in migen?
-
Hello! I wanted to ask if there was any interest from the maintainers in adding a [COBS](https://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing) encoder and decoder to this library.
I've b…