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This strictly isn't a problem with picorv32, but with the RISCV toolchain. However I'll start here as I suspect many might hit this from here.
Environment: a fully updated Ubuntu 21.10/AMD64
Co…
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In picosoc.v, I noticed that the read data outputs (rdata1, rdata2) of "module picosoc_regs" are combination out, directly implemented using wire "assign".
Does this mean the read delay of picosoc_…
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iceprog toplevel.bin in Murax of VexRiscv (gateware)
iceprog firmware.bin in picorv32
can do them both?
burn the gateware then firmware
then I can add instruction in Murax and modify riscv gcc com…
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Hello,
I'm currently working with LiteX on a Muselab IceSugar board equipped with a Lattice iCE40U5k FPGA. I've encountered an unexpectedly high latency when reading from the Wishbone bus. I've i…
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I am using the tutorial.bit and tutorial.tcl files under \PYNQ-RISC-V\riscvonpynq\picorv32\tut\gold, As per the skipping steps in Notebook mentioned under https://github.com/drichmond/RISC-V-On-PYNQ/b…
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It seems the checker is wrong as both `picorv32` and `cv32e40x` get failing assertions and the traces look weird.
Otherwise, I might be wrong and have misunderstood something here.
If anyone else cu…
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I just replace the picosoc.v with picoramsoc.v in the directory /picosoc, and remove the unused ports in hx8kdemo.v and disconnect the spiflash in hx8kdemo_tb.v before simulation. Using the same hex f…
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hello,
plz can any one suggest me,how to check the addition of 2 numbers using picorv32.i mean now succesfully i hv compiled and able to run the whole picorv32 respository now i want to check by, by …
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A few changes are needed for successful synthesis by the legacy Xilinx ISE toolchain:
- xst incorrectly implements the register file with ENABLE_REGS_DUALPORT = 1, but ENABLE_REGS_DUALPORT = 0 work…