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Such as results of CoreMark and Dhrystone. That would be very useful, thanks!
I find a picture from Western Digital, but I don't know why SweRV(2-wide superscalar in-order cpu) has higher score tha…
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Hi Olof,
I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires driven?
Thanks in advanc…
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SweRV C++ output has a bunch of code like this
```
a = a & 0xfffffff0 | something;
a = a & 0xffffff0f | something_else;
...
a = a & 0x0fffffff | something_else2;
```
These are f…
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Usually, we hide all the assertion code in RTL from frontend tools like synthesis/lint etc.
The core has used below define to add guard against asserts. So we could "not define" this and asserts shou…
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**$ fusesoc run --target=sim swervolf**
INFO: Preparing ::cdc_utils:0.1
INFO: Downloading fusesoc/cdc_utils from github
INFO: Preparing chipsalliance.org:cores:SweRV_EH1:1.8
INFO: Downloading chip…
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Hi @jrahmeh,
I am trying to add a floating point unit with EH2 as a `out of pipe` just like division is implemented. Just want to have some guidance or points to keep in mind.
I have generated the e…
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How **div/rem** instruction is handled in quasar core when it comes just before **ecall** (for test finishing)?
while no **div_wren** or **cancel** signal is raised for the correct result/data of the…
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Code has hand-instantiated clock gating cells which are defined in below library.
swerv_el2/rtl/lib/beh_lib.sv
module `TEC_RV_ICG
Generally such clock gates are not synthesized, rather a specif…
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The design does not synthesize.
Version of the FPGA repository: `3b67dc9441f44708b7800ae90c7ef0149e295f72`
Version of the swerv_eh1 repository: `48f01f101eeeb8c75013afb4546e01b0fda08984`
```
*…
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After downloading the package, and getting ssp running, I attempt to download the docker image for the SweRV emulator.
So I run the command:
ssp download
The ssp.yaml file contains the key:
…