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I am attempting to use Verilator 5.015 for RTL simulation, and I've run into issues related to Verilator's support for SystemVerilog Assertions (SVA).
**Issues Faced**:
1. Verilator does not su…
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yield statements seem like wait or join in Verilog.
I would like for Cocotb has more functionalities for event-waiting.
Systemverilog has three different kinds of join keywords, join, join_any, and j…
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```
When running ReSim examples, ModelSim can successfully compile the library and
the example source code but fail to load the design.
ModelSim only reports "Error loading the design" but does not…
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```
When running ReSim examples, ModelSim can successfully compile the library and
the example source code but fail to load the design.
ModelSim only reports "Error loading the design" but does not…
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In `testsuite/bsc.misc/divmod/` there are tests for division-by-zero behavior in Bluesim and Verilog backends. The Bluesim tests are expected to raise SIGFPE. For wide bit vectors, this is achieved …
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Hello!
It appears that after fixing #5472 there was a regression and now the simulation stops after executing the `initial` process even in a `module` block (not only in `program` block).
Expect…
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## Steps to reproduce the issue
Hi, I noticed the following miscompilation bug. Not sure if it is considered interesting or not:
Consider the following Verilog program:
```
> cat small.v
mo…
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```
When running ReSim examples, ModelSim can successfully compile the library and
the example source code but fail to load the design.
ModelSim only reports "Error loading the design" but does not…
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While “legacy” integration is easily dismissed as a “detail”, in practice it is anything but. Getting this right gives designers an easy on-boarding path to a particular technology. Getting it wro…
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> ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/functions.vh:44]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in ver…