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Is SystemVerilog support planned in Digital?
Thanks
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```
When running ReSim examples, ModelSim can successfully compile the library and
the example source code but fail to load the design.
ModelSim only reports "Error loading the design" but does not…
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> ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/functions.vh:44]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in ver…
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## Steps to reproduce the issue
Hi, I noticed the following miscompilation bug. Not sure if it is considered interesting or not:
Consider the following Verilog program:
```
> cat small.v
mo…
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```
When running ReSim examples, ModelSim can successfully compile the library and
the example source code but fail to load the design.
ModelSim only reports "Error loading the design" but does not…
-
```
When running ReSim examples, ModelSim can successfully compile the library and
the example source code but fail to load the design.
ModelSim only reports "Error loading the design" but does not…
-
While “legacy” integration is easily dismissed as a “detail”, in practice it is anything but. Getting this right gives designers an easy on-boarding path to a particular technology. Getting it wro…
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In some cases yosys produces a warning like this:
```
Warning: converting real value 7.960000e+01 to binary 80 at foo.sv:19.
```
The warning is correct and I expected that it would do that without…
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In `testsuite/bsc.misc/divmod/` there are tests for division-by-zero behavior in Bluesim and Verilog backends. The Bluesim tests are expected to raise SIGFPE. For wide bit vectors, this is achieved …
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Hi,
From the Documentation, it was found that the functional coverage is from the ISS Simulation-flow
![image](https://user-images.githubusercontent.com/45351688/191110708-c3cbb3cc-8b9f-4b90-935…